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c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - s e p . , 2 0 0 9 a p w 7 1 1 6 w w w . a n p e c . c o m . t w 1 a n p e c r e s e r v e s t h e r i g h t t o m a k e c h a n g e s t o i m p r o v e r e l i a b i l i t y o r m a n u f a c t u r a b i l i t y w i t h o u t n o t i c e , a n d a d v i s e c u s t o m e r s t o o b t a i n t h e l a t e s t v e r s i o n o f r e l e v a n t i n f o r m a t i o n t o v e r i f y b e f o r e p l a c i n g o r d e r s . 3 - i n - 1 d u a l p w m b u c k a n d l i n e a r d d r p o w e r c o n t r o l l e r f e a t u r e s a p p l i c a t i o n s g e n e r a l d e s c r i p t i o n d d r m e m o r y a n d m c h p o w e r s u p p l y p r o v i d e s y n c h r o n o u s r e c t i f i e d b u c k p w m c o n t r o l l e r s f o r v d d q a n d v m c h i n t e g r a t e d p o w e r f e t s w i t h v t t r e g u l a t o r s o u r c e / s i n k u p t o 2 . 0 a d r i v e l o w c o s t n - c h a n n e l p o w e r m o s f e t s i n t e r n a l 0 . 8 v r e f e r e n c e v o l t a g e f o r a d j u s t a b l e v d d q a n d v m c h t h e r m a l s h u t d o w n v t t t r a c k s a t h a l f t h e r e f e r e n c e v o l t a g e f i x e d s w i t c h i n g f r e q u e n c y o f 2 5 0 k h z f o r v d d q a n d v m c h o v e r - c u r r e n t p r o t e c t i o n a n d u n d e r - v o l t a g e p r o t e c t i o n f o r v d d q a n d v m c h f u l l y c o m p l i e s w i t h a c p i p o w e r s e q u e n c i n g s p e c i f i c a t i o n s 1 8 0 d e g r e e s p h a s e s h i f t b e t w e e n v d d q a n d v m c h p o w e r - o k f u n c t i o n f o r v d d q a n d v m c h f a s t t r a n s i e n t r e s p o n s e - m a x i m u m d u t y c y c l e 9 0 % - h i g h - b a n d w i d t h e r r o r a m p l i f i e r s i m p l e s i n g l e - l o o p c o n t r o l d e s i g n - v o l t a g e m o d e p w m c o n t r o l - e x t e r n a l c o m p e n s a t i o n e x t e r n a l s o f t - s t a r t f o r v d d q a n d v m c h s h u t d o w n f u n c t i o n f o r v d d q / v t t a n d v m c h t h e r m a l l y e n h a n c e d t s s o p - 2 4 p p a c k a g e l e a d f r e e a n d g r e e n d e v i c e s a v a i l a b l e ( r o h s c o m p l i a n t ) t h e a p w 7 1 1 6 i n t e g r a t e s d u a l p w m b u c k c o n t r o l l e r s a n d a n i n t e r n a l l i n e a r r e g u l a t o r f o r d d r m e m o r y a n d m c h p o w e r s o l u t i o n . t h e t w o s y n c h r o n o u s p w m b u c k c o n t r o l - l e r s d r i v e f o u r n - c h a n n e l m o s f e t s f o r d d r m e m o r y s u p - p l y v o l t a g e ( v d d q ) a n d m c h r e g u l a t o r . t h e i n t e r n a l r e g u - l a t o r i s d e s i g n e d t o t r a c k a t t h e h a l f o f t h e r e f e r e n c e v o l t - a g e w i t h s o u r c i n g a n d s i n k i n g c u r r e n t f o r d d r m e m o r y t e r m i n a t i o n r e g u l a t o r ( v t t ) . t h e a p w 7 1 1 6 u s e s t h e l a t c h e d b u f _ c u t s i g n a l a n d t h e p o r o f t h e b o o t t o c o m p l y w i t h a c p i p o w e r s e q u e n c i n g s p e c i f i c a t i o n s . t h e t w o p w m r e g u l a t o r s a l s o p r o v i d e p o k s i g n a l s t o i n d i c a t e t h a t t h e r e g u l a t o r s a r e g o o d . t h e d e - v i c e a l s o h a s t h e p h a s e s h i f t f u n c t i o n b e t w e e n t h e t w o p w m c o n t r o l l e r s . t h e p r o t e c t i o n f u n c t i o n s o f t h e t w o p w m c o n t r o l l e r s i n c l u d e o v e r - c u r r e n t p r o t e c t i o n , u n d e r - v o l t a g e p r o t e c t i o n , a n d e x t e r n a l s o f t - s t a r t f u n c t i o n . t h e v t t r e g u - l a t o r p r o v i d e s 2 a s i n k i n g a n d s o u r c i n g c u r r e n t - l i m i t f u n c - t i o n a n d a l s o h a s t h e r m a l s h u t d o w n p r o t e c t i o n . t h e t s s o p - 2 4 p p a c k a g e w i t h a c o p p e r p a d p r o v i d e s e x c e l l e n t t h e r m a l i m p e d a n c e i s a v a i l a b l e . p i n c o n f i g u r a t i o n t s s o p - 2 4 p ( t o p v i e w ) gnd bottom side pad phase1 lgate1 vcc boot ugate1 buf_cut comp2 lgate2 ugate2 phase2 gnd pok1 comp1 fb1 vtt vttgnd ss1/en1 agnd vddq refsen vttfb ss2/en2 fb2 pok2 1 3 2 4 6 5 7 9 8 10 12 11 24 22 23 21 19 20 18 16 17 15 13 14
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - s e p . , 2 0 0 9 a p w 7 1 1 6 w w w . a n p e c . c o m . t w 2 o r d e r i n g a n d m a r k i n g i n f o r m a t i o n symbol parameter rating unit v cc vcc to a gnd - 0.3 to 6 v v boot boot to agnd - 0.3 to 14 v ugate drive ugate1, ugate2 to gnd dc voltage <100ns pulse width - 0.3 to vboot+0.3 - 4 to vboot+2 v lgate drive l gate1, l gate2 to gnd dc voltage <100ns pulse width - 0.3 to vcc+0.3 - 4 to vcc +2 v phase phase1, phase2 to gnd dc voltage <100ns pulse width - 0.3 to 14 - 4 to 16 v io input/output pins to agnd pins 1 - 3, 5 - 6, 8 - 14, 18 - 19, 24 - 0.3 to 14 v i vtt vtt output current +/ - 2a a gnd gnd , vttgnd to a gnd - 0.3 to +0 .3 v t j maximum junction temperature +150 c t stg storage temperature range - 65 to +150 c t l lead soldering temperature, 10 seconds 260 c a b s o l u t e m a x i m u m r a t i n g s ( n o t e 1 ) n o t e 1 : a b s o l u t e m a x i m u m r a t i n g s a r e t h o s e v a l u e s b e y o n d w h i c h t h e l i f e o f a d e v i c e m a y b e i m p a i r e d . e x p o s u r e t o a b s o l u t e m a x i m u m r a t i n g c o n d i t i o n s f o r e x t e n d e d p e r i o d s m a y a f f e c t d e v i c e r e l i a b i l i t y . n o t e : a n p e c l e a d - f r e e p r o d u c t s c o n t a i n m o l d i n g c o m p o u n d s / d i e a t t a c h m a t e r i a l s a n d 1 0 0 % m a t t e t i n p l a t e t e r m i n a t i o n f i n i s h ; w h i c h a r e f u l l y c o m p l i a n t w i t h r o h s . a n p e c l e a d - f r e e p r o d u c t s m e e t o r e x c e e d t h e l e a d - f r e e r e q u i r e m e n t s o f i p c / j e d e c j - s t d - 0 2 0 d f o r m s l c l a s s i f i c a t i o n a t l e a d - f r e e p e a k r e f l o w t e m p e r a t u r e . a n p e c d e f i n e s ? g r e e n ? t o m e a n l e a d - f r e e ( r o h s c o m p l i a n t ) a n d h a l o g e n f r e e ( b r o r c l d o e s n o t e x c e e d 9 0 0 p p m b y w e i g h t i n h o m o g e n e o u s m a t e r i a l a n d t o t a l o f b r a n d c l d o e s n o t e x c e e d 1 5 0 0 p p m b y w e i g h t ) . APW7116 package code r : tssop-24p operating ambient temperature range e : - 20 to 70 o c handling code tr : tape & reel assembly material g : halogen and lead free device APW7116 r : APW7116 xxxxx xxxxx - date code handling code temp erature range package code assembly material r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s range symbol parameter min. typ. max. unit v cc vcc to a gnd 4.5 5 5.5 v v boot boot to agnd 10.8 12 13.2 v v in power input voltage of pwm controllers to agnd 2.97 5 5.5 v v ddq vddq to agnd 0.8 - 2.5 v v mch vmch to agnd 0.8 - 1.5 v v refsen v refsen t o agnd 1.8 - 2.5 v
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - s e p . , 2 0 0 9 a p w 7 1 1 6 w w w . a n p e c . c o m . t w 3 range symbol parameter min. typ. max. unit i vtt vtt output current - 1.8 - 1.8 a t j operating junction temperature - 20 - 125 c t a operating ambient temperature - 20 - 70 c r e c o m m e n d e d o p e r a t i n g c o n d i t i o n s ( c o n t . ) e l e c t r i c a l c h a r a c t e r i s t i c s o p e r a t i n g c o n d i t i o n s : v c c = 5 v , b o o t = 1 2 v , t a = - 2 0 c t o 7 0 c , u n l e s s o t h e r w i s e s p e c i f i e d . APW7116 symbol parameter test conditions min. typ. max. unit supply current vcc supply current (s0 mode) s0 mode, ugates, lgates open - 5 10 ma vcc supply current (s3 mode) s3 mode, ugates, lgates open - 2.5 5 ma i vcc vcc supply current (s5 mod e) s5 mode, ugates, lgates open - 0.5 1.0 ma boot supply current (s0 mode) s0 mode, ugates, lgates are switching - 1.5 5 m a i boot boot supply current (s3 mode) s3 mode, ugates, lgates are switching - 1 5 ma power - on - reset threshold vcc rising 4.0 4.2 4.4 v v cc vcc power - on - re set threshold vcc falling 3. 8 3.9 4.0 v vboot rising 10.0 10.2 10.4 v v boot boot power - on - reset threshold vboot falling 9 .1 9.3 9.5 v thermal shutdown t sd thermal shutdown (note2) - 150 - c t sdhys thermal shutdown hyster esis (note2) - 50 - c oscillator (pwm1 and pwm2) f osc oscillator frequency 225 2 50 275 khz d v osc oscillator ramp amplitude (note2) - 1.9 - v duty duty cycle range (note2) 0 - 90 % reference volta g e reference voltage - 0.8 - v reference voltage accuracy - 1.0 - +1.0 % v ref1 load regulation i vddq = 0 to 10a - 0.2 - % reference voltage - 0.8 - v reference voltage accuracy - 1.0 - +1.0 % v ref2 load regulation i gmch = 0 to 5a - 0.2 - % power - okay (pok1 and pok2) v poklt low threshold fb f alls % of v ref 83 - - % v pokht high threshold fb reaches % of v ref - - 90 % i lkg leakage current v pok = 5v - - 1 m a v pokol pok low voltage i pok = 2ma - 0.16 0.3 v
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - s e p . , 2 0 0 9 a p w 7 1 1 6 w w w . a n p e c . c o m . t w 4 e l e c t r i c a l c h a r a c t e r i s t i c s ( c o n t . ) APW7116 symbol parameter test conditions min. typ. max. unit error amplifier (pwm1 and pwm2) open loop gain (note2) r l =10k w to gnd - 75 - d b open loop bandwidth (note 2 ) r l =10k w to gnd, c l =100pf - 12 - m h z slew rate (note2) r l =10k w to gnd, c l =1 00pf - 8 - v / m s output high source current comp = 2.5v - 40 - m a output low sink current comp = 2.5v - 40 - ma protection and monitor (pwm1 and pwm2) i ocset phase source current 90 110 130 m a v ocp ocp reference voltage 0.17 0.2 0.23 v fb under voltage level output falls % of v ref 55 60 65 % i ss soft - start charge current 8 11 14 m a ss/en shutdown threshold - - 0.2 v vtt regulator i out = - 10m a to 10m a v ref sen = 2.5v - 20 - 20 m v vtt vtt output voltage i out = - 10ma to 10ma v ref sen = 1.8v - 13 - - 13 m v lo ad regulation i out = - 2a to 2a - 1 - 1 % line regulation vddq = 1.8v to 2.5v - - 0.2 % r refsen refsen input resistance (note 2 ) - 50 - k w vttfb hysteresis (note 2 ) % of refsen - 0.1 - % vtt source current limit 2 2.5 3 a ilimvtt vtt sink current lim it 2 2.5 3 a r ds(on) internal power fets r ds(on) - 0.3 0.4 w internal soft - start interval (note 2 ) - 0.5 - ms buf_cut control v buf _ cuth buf_cut input logic high 2.0 - - v v buf _ cutl buf_cut input logic low - - 0.8 v i buf _ cut buf_cut input current 1 3 5 m a g ate d rivers ugate1 source boot=12v, ugate1=2v 1 1.5 - a ugate1 sink vcc=5v, ugate1=2v - 1.2 1.8 w lgate1 source boot=12v, lgate1=2v 1.7 2.5 - a lgate1 sink vcc=5v, lgate1=2v - 0.45 0.675 w ugate2 source boot=12v, ugate2=2v 0.7 1 - a ugate2 sink vcc=5v, ugate2=2v - 2.3 3.45 w lgate2 source boot=12v, lgate2=2v 1.3 1.9 - a lgate2 sink vcc=5v, lgate2=2v - 0.6 0.9 w dead time (note 2 ) - 20 - ns n o t e 2 : g u a r a n t e e d b y d e s i g n , n o t t e s t e d i n p r o d u c t i o n . o p e r a t i n g c o n d i t i o n s : v c c = 5 v , b o o t = 1 2 v , t a = - 2 0 c t o 7 0 c , u n l e s s o t h e r w i s e s p e c i f i e d .
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - s e p . , 2 0 0 9 a p w 7 1 1 6 w w w . a n p e c . c o m . t w 5 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s b o o t - u g a t e 1 v o l t a g e ( v ) source current (a) u g a t e 1 v o l t a g e ( v ) sink current (a) s i n k c u r r e n t v s . u g a t e 1 v o l t a g e s o u r c e c u r r e n t v s . b o o t - u g a t e 1 v o l t a g e l g a t e 1 v o l t a g e ( v ) v c c - l g a t e 1 v o l t a g e ( v ) sink current (a) source current (a) s i n k c u r r e n t v s . l g a t e 1 v o l t a g e s o u r c e c u r r e n t v s . v c c - l g a t e 1 v o l t a g e 0 2 4 6 8 10 12 0 0.5 1 1.5 2 2.5 3 3.5 4 0 1 2 3 4 5 0 2 4 6 8 10 12 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0 1 2 3 4 5 0 1 2 3 4 5 6 7 0 1 2 3 4 5 0 2 4 6 8 10 12 0 0.5 1 1.5 2 2.5 3 b o o t - u g a t e 2 v o l t a g e ( v ) source current (a) s o u r c e c u r r e n t v s . b o o t - u g a t e 2 v o l t a g e 0 0.5 1 1.5 2 0 2 4 6 8 10 12 u g a t e 2 v o l t a g e ( v ) sink current (a) s i n k c u r r e n t v s . u g a t e 2 v o l t a g e
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - s e p . , 2 0 0 9 a p w 7 1 1 6 w w w . a n p e c . c o m . t w 6 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s ( c o n t . ) v t t l o a d c u r r e n t ( a ) d vtt voltage (v) temperature ( o c) fb voltage (mv) f b v o l t a g e v s . t e m p e r a t u r e d vtt voltage vs. vtt load current temperature ( o c) ocset current ( m a) o c s e t c u r r e n t v s . t e m p e r a t u r e temperature ( o c) switching frequency (khz) s w i t c h i n g f r e q u e n c y v s . t e m p e r a t u r e l g a t e 2 v o l t a g e ( v ) sink current (a) s i n k c u r r e n t v s . l g a t e 2 v o l t a g e v c c - l g a t e 2 v o l t a g e ( v ) source current (a) s o u r c e c u r r e n t v s . v c c - l g a t e 2 v o l t a g e 0 1 2 3 4 5 0 0.5 1 1.5 2 2.5 3 0 1 2 3 4 5 0 1 2 3 4 5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 14 fb1 fb2 790 792 794 796 798 800 802 -40 -20 0 20 40 60 80 100 120 140 105 106 107 108 109 110 111 112 113 -40 -20 0 20 40 60 80 100 120 140 160 230 235 240 245 250 255 260 -40 -20 0 20 40 60 80 100 120 140 160
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - s e p . , 2 0 0 9 a p w 7 1 1 6 w w w . a n p e c . c o m . t w 7 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s ( c o n t . ) t i m e ( 1 0 m s / d i v ) t i m e ( 1 0 m s / d i v ) v d d q & v t t p o w e r u p 1 v d d q & v m c h p o w e r u p t i m e ( 1 0 m s / d i v ) v d d q & v t t p o w e r u p 2 t i m e ( 1 m s / d i v ) p h a s e s h i f t ss2 (2v/div) vddq (1v/div) vddq pin= vddq output vtt (1v/div) ss1 (2v/div) vddq (2v/div) boot (5v/div) vddq pin= external supply vtt (1v/div) ug1 (10v/div) lg1 (5v/div) ug2 (10v/div) lg2 (5v/div) ss1 (2v/div) vddq (1v/div) v m c h ( 1 v / d i v ) ss1 (2v/div)
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - s e p . , 2 0 0 9 a p w 7 1 1 6 w w w . a n p e c . c o m . t w 8 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s ( c o n t . ) t i m e ( 1 0 m s / d i v ) t i m e ( 1 0 m s / d i v ) d i s a b l e v d d q e n a b l e v d d q t i m e ( 1 0 m s / d i v ) e n a b l e v m c h t i m e ( 1 0 m s / d i v ) d i s a b l e v m c h pok1 (5v/div) vddq (2v/div) ss1 (2v/div) ug1 (10v/div) pok1 (5v/div) vddq (2v/div) ss1 (2v/div) ug1 (10v/div) pok1 (5v/div) vmch (2v/div) ss1 (2v/div) ug1 (10v/div) pok1 (5v/div) vmch (2v/div) ss1 (2v/div) ug1 (10v/div)
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - s e p . , 2 0 0 9 a p w 7 1 1 6 w w w . a n p e c . c o m . t w 9 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s ( c o n t . ) t i m e ( 2 0 n s / d i v ) t i m e ( 2 0 n s / d i v ) u g 1 f a l l i n g u g 1 r i s i n g t i m e ( 2 0 n s / d i v ) u g 2 r i s i n g t i m e ( 2 0 n s / d i v ) u g 2 f a l l i n g ug1 (5v/div) phase1 (5v/div) lg1 (5v/div) ug1 (5v/div) phase1 (5v/div) lg1 (5v/div) ug2 (5v/div) phase2 (5v/div) lg2 (5v/div) ug2 (5v/div) phase2 (5v/div) lg2 (5v/div)
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - s e p . , 2 0 0 9 a p w 7 1 1 6 w w w . a n p e c . c o m . t w 1 0 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s ( c o n t . ) t i m e ( 5 m s / d i v ) t i m e ( 5 m s / d i v ) s 3 t o s 0 s 0 t o s 3 t i m e ( 2 0 m s / d i v ) v d d q u v p t i m e ( 2 0 m s / d i v ) v m c h u v p vddq (2v/div) vmch (1v/div) vtt (1v/div) buf_cut (5v/div) vddq (2v/div) vmch (1v/div) vtt (1v/div) buf_cut (5v/div) comp1 (2v/div) ss1 (5v/div) vref1 (0.5v/div) ug1 (10v/div) comp2 (2v/div) ss2 (5v/div) vref2 (0.5v/div) ug2 (10v/div)
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - s e p . , 2 0 0 9 a p w 7 1 1 6 w w w . a n p e c . c o m . t w 1 1 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s ( c o n t . ) t i m e ( 1 0 m s / d i v ) t i m e ( 1 0 m s / d i v ) v m c h o c p v d d q o c p t i m e ( 2 0 m s / d i v ) v t t l o a d t r a n s i e n t t i m e ( 0 . 1 m s / d i v ) v d d q l o a d t r a n s i e n t r ocset =6k mosfet=apw2014 ug1 (10v/div) ss1 (5v/div) vddq (2v/div) il (10a/div) r ocset =4k mosfet=apw2014 ug1 (10v/div) ss1 (5v/div) vmch (2v/div) il (10a/div) vddq (0.1v/div) vmch (0.1v/div) vtt(0.1v/div) vtt outout current (2a/div) vddq (0.2v/div) vmch (0.1v/div) vtt(0.1v/div) vddq outout current (10a/div)
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - s e p . , 2 0 0 9 a p w 7 1 1 6 w w w . a n p e c . c o m . t w 1 2 t y p i c a l o p e r a t i n g c h a r a c t e r i s t i c s ( c o n t . ) t i m e ( 0 . 1 m s / d i v ) v m c h l o a d t r a n s i e n t vddq (0.1v/div) vmch (0.2v/div) vtt(0.1v/div) vmch outout current (10a/div) pin no. name function 1 comp1 these pins are the output of error amplifiers of their respective regulators. they are used to set the compensation components. 2 fb1 these pins are the inverting input of the error amplifiers of their respective regulator s. they are used to set the output voltage and the compensation components. if the fb voltage is under 60% of reference voltage, it will cause the under - voltage protection and turn off all regulators because of the short circuit or other influence. remove the error condition and restart the vcc voltage, the device will enable again. 3 ss1 connect a capacitor to the gnd for setting the soft - start time. use an open drain logic signal to pull the ss/en pin low to disable the respective output, leave open to enable the respective output. 4 vttgnd vtt return. connect to copper plane carrying vtt return current. the trace connecting to this pin must be able to carry 2a. 5 vtt vtt regulator output. 6 vddq power input for vtt regulator. 7 agnd analog ground. c ompensation components and the soft - start capacitors connect to this ground. 8 vttfb vtt regulation pin for closed loop regulation. 9 refsen reference voltage input of vtt regulator. vtt will be regulated to 1/2 of this voltage. connect to point of load. 10 fb2 these pins are the inverting input of the error amplifiers of their respective regulators. they are used to set the output voltage and the compensation components. if the fb voltage is under 60% of reference voltage, it will cause the under - volta ge protection and turn off all regulators because of the short circuit or other influence. remove the error condition and restart the vcc voltage, the device will enable again. 11 ss2 connect a capacitor to the gnd for setting the soft - start time. use an open drain logic signal to pull the ss/en pin low to disable the respective output, leave open to enable the respective output. p i n d e s c r i p t i o n
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - s e p . , 2 0 0 9 a p w 7 1 1 6 w w w . a n p e c . c o m . t w 1 3 pin no. name function 12 pok2 these pins are open - drain pull - down devices. when respective fb falls 83% of reference voltage, the output is pulled low. when respective fb reaches 90% reference voltage, the output is pulled high, for power is okay. 13 p ok1 these pins are open - drain pull - down devices. when respective fb falls 83% of reference voltage, the output is pulled low. when respective fb reaches 90% reference voltage, the output is pulled high, for power is okay. 14 phase a resistor (rocset) is c onnected between this pin and the drain of the low - side mosfet will determine the over current limit of pwm conve r ter. 15 gnd this pin is the power ground pin for the gate drivers. 16, 23 lgate these pins provide the gate drivers for the lower mosfets of vddq and vmch. 17 ugate2 these pins provide the gate drivers for the upper mosfets of vddq and vmch. 18 buf_cut active high control signal to activate s3 sleep state. buf_cut is pulled low by internal 3 m a current source. 19 comp2 these pins are the output of error amplifiers of their respective regulators. they are used to set the compensation components. 20 vcc power supply input pin. connect a nominal 5v power supply to this pin for control circuit a nd lower gate drivers. 21 boot upper gate drivers input supply. 22 ugate1 these pins provide the gate drivers for the upper mosfets of vddq and vmch. 24 phase1 a resistor (rocset) is connected between this pin and the drain of the low - side mosfet will d etermine the over current limit of pwm conve r ter. p i n d e s c r i p t i o n ( c o n t . )
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - s e p . , 2 0 0 9 a p w 7 1 1 6 w w w . a n p e c . c o m . t w 1 4 b l o c k d i a g r a m power - on - reset and logic control gate control logic 1 oscillator v ref 1 0.8v vcc boot ss1/ en1 ss2/ en2 pok1 comp1 comp2 fb1 fb2 agnd vttgnd vttfb vtt refsen gnd lgate2 ugate2 ugate1 lgate1 11 m a 11 m a pok2 buf_cut phase1 phase2 vddq v ref 2 0.8v 83%~90%v ref 1 83%~90%v ref2 180 phase shift 110 m a 0.2v 110 m a 0.2v 60%v r ef 1 60%v ref2 uvp comparator uvp comparator gate control logic 2
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - s e p . , 2 0 0 9 a p w 7 1 1 6 w w w . a n p e c . c o m . t w 1 5 t y p i c a l a p p l i c a t i o n c i r c u i t 12v 5vdual filtered 5vdual or 3.3v vddq vmch vtt vddq vmch comp1 fb1 comp2 fb2 pok1 ss1/en1 ss2/en2 agnd vttgnd vttfb vtt lgate2 ugate2 lgate1 ugate1 APW7116 vcc boot phase1 phase2 vddq refsen gnd pok2 pull high voltage buf_cut 1 m f 2r2 1 m f 1500 m f 1 m f 1 m h/10a 0.1 m f 4.7nf 2r2 2200 m f 2200 m f 2r2 0r 2r2 0r apm2509n apm2506n 1.8 m h 1n4148 1n4148 1n4148 1500 m f 1 m f 1.8 m h 1000 m f 1000 m f 4.7nf 2r2 apm2014n apm2014n 0.1 m f 1 m f 470 m f 0.1 m f 0.1 m f 2.37k 8 100nf 10n 20k 6.8nf 2.2k 8 100nf 10n 20k 6.8nf 10k 10k en2 en1 2n7002 2n7002 2.5k 1.13k 6.2k 8.1k 470 m f filtered 5vdual
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - s e p . , 2 0 0 9 a p w 7 1 1 6 w w w . a n p e c . c o m . t w 1 6 time voltage t2 t 0 ss1&2 vddq&vmch fb1&2 vtt t3 1v 2v t 1 f u n c t i o n d e s c r i p t i o n f i g u r e 1 . s o f t - s t a r t i n t e r v a l (11ua) i v 1 c 2 t 3 t t ss ss s s = - = ms 5 . 0 0 t 1 t = - w h e r e : c s s = e x t e r n a l s o f t - s t a r t c a p a c i t o r i s s = s o f t - s t a r t c h a r g c u r r e n t s o f t - s t a r t / e n a b l e t h e v d d q a n d v m c h r e g u l a t o r s h a v e i n d e p e n d e n t s o f t - s t a r t c o n t r o l a n d s h u n d o w n f u n c t i o n . c o n n e c t a c a p a c i t o r f r o m e a c h s s p i n t o t h e g n d t o s e t t h e s o f t - s t a r t i n t e r v a l o f t h e v d d q a n d v m c h a n d a n o p e n d r a i n l o g i c s i g n a l f o r e a c h s s / e n p i n t o e n a b l e o r d i s a b l e t h e r e s p e c t i v e o u t p u t . f i g u r e 1 s h o w s t h e s o f t - s t a r t i n t e r v a l . a t t 0 , t h e v c c a n d b o o t v o l t o g e a r e a b o v e t h e i r p o r t r i p p o i n t s , a 1 1 m a c u r - r e n t s o u r c e s t a r t s t o c h a r g e t h e c a p a c i t o r a n d t h e v t t s t a r t s i t ? s i n t e r n a l s o f t - s t a r t i n t e r v a l . t h e s o f t - s t a r t i n t e r v a l o f v t t i s a b o u t 5 0 0 m s . w h e n t h e s s r e a c h e s 1 v , t h e i n t e r n a l r e f e r e n c e v o l t a g e s t a r t s t o r i s e a n d f o l l o w s t h e s s . u n t i l t h e s s r e a c h e s a b o u t 2 v a t t 3 , t h e i n t e r n a l r e f e r - e n c e c o m p l e t e s t h e s o f t - s t a r t i n t e r v a l a n d r e a c h e s t o 0 . 8 v . t h e s o f t - s t a r t o f v m c h i s t h e s a m e a s t h e v d d q . t h i s m e t h o d p r o v i d e s a r a p i d a n d c o n t r o l l e d o u t p u t v o l t - a g e r i s e . p o w e r - o k a y t h e p o w e r - o k a y f u n c t i o n m o n i t o r s t h e v d d q a n d v m c h a n d d r i v e s l o w t o i n d i c a t e a f a u l t . w h e n a f a u l t c o n d i t i o n , s u c h a s o v e r - c u r r e n t , s h o r t - c i r c u i t , t h e r m a l s h u t d o w n i s o c c u r r e d , a n d t h e v d d q o r v m c h f a l l s t o 8 3 % o f i t ? s n o m i - n a l v o l t a g e , t h e p o k i s p u l l e d l o w . w h e n t h e v d d q o r v m c h r e a c h e s t o 9 0 % o f i t ? s n o m i n a l v o l t a g e , t h e p o k i s p u l l e d h i g h . s i n c e t h e p o k i s a n o p e n - d r a i n d e v i c e , c o n - n e c t i n g a 1 0 k w r e s i s t o r t o a p u l l h i g h v o l t a g e i s n e c e s s a r y . time voltage vddq pok1 83% 90% fb1 f i g u r e 2 . p o w e r - o k a y f u n c t i o n o v e r - c u r r e n t p r o t e c t i o n a r e s i s t o r ( r o c s e t ) i s c o n n e c t e d b e t w e e n t h e p h a s e p i n a n d t h e d r a i n o f t h e l o w - s i d e m o s f e t w i l l d e t e r m i n e t h e o v e r - c u r r e n t l i m i t . a n i n t e r n a l l y g e n e r a t e d 1 1 0 m a c u r - r e n t s o u r c e w i l l f l o w t h r o u g h t h i s r e s i s t o r , c r e a t i n g a v o l t - a g e d r o p . w h e n t h e v o l a t g e a c r o s s t h e l o w - s i d e m o s f e t e x c e e d s t h e v o l t a g e a c r o s s t h e r o c s e t m i n u s ocp v , t h e o c p i s d e t e c t e d . t h e o c p f u n c t i o n w i l l t r i p a t a p e a k i n d u c t o r c u r r e n t , t h e t h r e s h o l d o f t h e o v e r - c u r r e n t l i m i t i s t h e r e f o r e g i v e n b y : mosfet lower the of r v i r i ds(on) ocp ocset ocset limit - = for the over-current is never occurred in the normal op- erating load range; the variation of all parameters in the above equation should be determined. the mosfet r ds(on) is varied by temperature and gate to source voltage, the user should determine the maxi- mum r ds(on) in manufacturer?s datasheet. the minimum i ocset (90 m a), maximum vocp (230mv) and m inimum r ocset should be used in the above equation. use 1% or better resistor for r ocset is recommended. note that the ilimit is the current flow through the up- per mosfet; ilimit must be greater than maximum out- put current add the half of inductor ripple current. a n o v e r - c u r r e n t c o n d i t i o n w i l l r e p e a t t h e s o f t - s t a r t f u n c - t i o n 3 t i m e s ; i f t h e o v e r - c u r r e n t c o n d i t i o n i s n o t r e m o v e d d u r i n g t h e 3 t i m e s s o f t - s t a r i n t e r v a l , a n d t h e n a l l r e g u l a - t o r s w i l l b e s h u t d o w n , a n d r e q u i r e a p o r o n e i t h e r o f v c c o r v b o o t t o r e s t a r t i c .
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - s e p . , 2 0 0 9 a p w 7 1 1 6 w w w . a n p e c . c o m . t w 1 7 f u n c t i o n d e s c r i p t i o n ( c o n t . ) time vddq ss1 vtt vmch pok1 il1 ss2 pok2 f i g u r e 3 . v d d q o v e r - c u r r e n t p r o t e c t i o n w a v e f o r m s n o t e t h a t t h e p a r a s t i c c a p a c i t o r f r o m p h a s e p i n t o t h e g n d w i l l d i s t o r t t h e p h a s e p i n s i g n a l a n d t h e c u r r e n t l i m i t w i l l b e l a r g e r t h a n s e t v a l u e . r e d u c e t h e p a r a s t i c c a p a c i t a n c e a s s m a l l a s p o s s i b l e t o m a k e t h e c u r r e n t l i m i t m e e t s e t v a l u e . o v e r - c u r r e n t p r o t e c t i o n ( c o n t . ) f i g u r e 4 . l o w - s i d e o v e r - c u r r e n t p r o t e c t i o n c i r c u i t r ds(on) + _ o.c.p. comparator il phase r ocset il 110ua 0.2v + _ i ocset v ocp v t t r e g u l a t o r t h e v t t r e g u l a t o r h a s t w o i n t e r n a l n - c h a n n e l f e t s t o p r o v i d e c u r r e n t s i n k a n d s o u r c e c a p a b i l i t y u p t o 2 a . t h e v t t r e g u l a t o r i s t r a c k e d a t t h e h a l f o f r e f s e n v o l t a g e b y t h e i n t e r n a l r e s i s t o r d i v i d e r . w h e n b o t h v c c a n d b o o t v o l t a g e s r e a c h t h e i r r i s i n g p o r t r i p p o i n t s , t h e s o f t - s t a r t o f t h e v t t s t a r t s r i s i n g ; t h e s o f t - s t a r t i n t e r v a l i s a b o u t 0 . 5 m s . t h e v t t r e g u l a t o r i s a c t i v a t e d o n l y i n s 0 m o d e ; i n s 3 m o d e , t h e v t t r e g u l a t o r i s n o t n e e d e d a n d t u r n e d o f f . t h e v t t r e g u l a t o r h a s 2 . 5 a s i n k a n d s o u r c e c u r r e n t l i m i t t o p r o t e c t t h e i n t e r n a l f e t s . w h e n c u r r e n t l i m i t i s o c c u r r e d , t h e r e g u l a t o r k e e p s t h e l o a d c u r r e n t a t 2 . 5 a . t h e d e v i c e p r o v i d e s a s o f t - s t a r t f u n c t i o n w h e n c u r r e n t l i m i t c o n d i t i o n i s r e l e a s e d . p h a s e s h i f t t h e a p w 7 1 1 6 h a s p h a s e s h i f t f u n c t i o n b e t w e e n t h e t w o p w m c o n v e r t e r s . t h e p h a s e d i f f e r e n c e i s r e l a t i v e t o t h e f a l l i n g e d g e s o f u g a t e 1 a n d u g a t e 2 a n d t h e p h a s e s h i f t i s f i x e d a t 1 8 0 d e g r e e s ( s e e f i g u r e 5 ) . h o w e v e r , t h e p h a s e s h i f t b e t w e e n t h e r i s i n g e d g e o f u g a t e 1 a n d u g a t e 2 , d e p e n d i n g o n t h e d u t y c y c l e s , t h e r i s i n g e d g e s m i g h t o v e r l a p , t h e r e f o r e , t h e u s e r s h o u l d c h e c k i t . t h e a d v a n t a g e o f p h a s e s h i f t i s t o a v o i d o v e r l a p p i n g t h e s w i t c h i n g c u r r e n t s p i k e s o f t h e t w o c h a n n e l s , o r i n t e r a c - t i o n b e t w e e n t h e c h a n n e l s ; i t a l s o r e d u c e s t h e r m s c u r - r e n t o f t h e i n p u t c a p a c i t o r s , a l l o w i n g f e w e r c a p s t o b e e m p l o y e d . f i g u r e 5 . p h a s e o f u g 2 w i t h r e s p e c t t o f a l l i n g e d g e o f u g 1 time voltage ugate1 ugate2 180 shift t h e r m a l s h u t d o w n w h e n t h e j u n c t i o n t e m p e r a t u r e e x c e e d s 1 5 0 c , t h e d e - v i c e s h u t d o w n t o p r o t e c t t h e d e v i c e f r o m d a m a g e . a f t e r t h e t e m p e r a t u r e d e c r e a s e s t o 1 0 0 c , t h e d e v i c e s t a r t s u p a g a i n . a c p i c o n t r o l l o g i c t h e b u f _ c u t s i g n a l a n d t w o p o w e r - o n - r e s e t t h r e s h - o l d s o n v c c a n d b o o t p i n s a r e u s e d t o d e t e r m i n e t h e o p e r a t i n g m o d e . t h e v c c a n d b o o t a r e s u p p l i e d b y e x t e r n a l s u p p l i e s 5 v d u a l a n d 1 2 v a t x . w h e n t h e v c c
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - s e p . , 2 0 0 9 a p w 7 1 1 6 w w w . a n p e c . c o m . t w 1 8 f u n c t i o n d e s c r i p t i o n ( c o n t . ) a c p i c o n t r o l l o g i c ( c o n t . ) a n d b o o t v o l t a g e a r e a b o v e t h e i r p o r r i s i n g t r i p p o i n t s , t h e d e v i c e i s e n a b l e d a n d e n t e r s t h e s 0 n o r m a l o p e r a t - i n g m o d e . t h e b u f _ c u t i s p u l l e d l o w b y i n t e r n a l c u r r e n t s o u r c e . p u l l t h e b u f _ c u t t o h i g h i n s 0 m o d e , t h e d e v i c e e n t e r s t h e s 3 s l e e p m o d e . i n s 3 m o d e , t h e o u t p u t v o l t - a g e s v t t a n d v m c h a r e d i s a b l e d a n d s u p p l y v o l t a g e 1 2 v a t x i s n o t s u p p l i e d t o t h e d e v i c e . w h e n b u f _ c u t i s p u l l e d l o w a n d t h e 1 2 v a t x i s e n a b l e d , t h e o p e r a t i n g m o d e w i l l b e b a c k t o s 0 m o d e . i f t h e 1 2 v a t x s u p p l y v o l t a g e i s r e m o v e d , t h e d e v i c e i s i n t o s 5 s h u t d o w n m o d e , a l l r e g u - l a t o r w i l l b e s h u t d o w n . n o t e t h a t t r a n s i t i o n f r o m s 3 t o s 5 i s n o t a l l o w e d . a t i m i n g d i a g r a m i s s h o w n i n f i g u r e 6 a n d a s t a t e t r a n s i t i o n s d i a g r a m i s s h o w n i n f i g u r e 7 .
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - s e p . , 2 0 0 9 a p w 7 1 1 6 w w w . a n p e c . c o m . t w 1 9 f u n c t i o n d e s c r i p t i o n ( c o n t . ) f i g u r 6 . a c p i t i m i n g d i a g r a m f i g u r e 7 . s t a t e t r a n s i t i o n s d i a g r a m s5 s3 s0 ic is off boot=h & buf_cut=l & boot=l buf_cut=l & vcc=h & vcc=l boot=h buf_cut=l & buf_cut=h buf_cut=l boot=h vcc=l vcc=l all regulators are on vmch & vtt are off all regulators are off buf_cut 12v 5vstby or 5vdual ss1 ss2 vddq vmch vtt pok1 pok2 s0 s3 s0 s5 por high threshold buf_cut high threshold buf_cut low threshold por low threshold 90%vddq 90%vmch 90%vmch 83%vddq 83%vmch ic is off 83%vmch
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - s e p . , 2 0 0 9 a p w 7 1 1 6 w w w . a n p e c . c o m . t w 2 0 a p p l i c a t i o n i n f o r m a t i o n 0.8v x ) r2 r1 1 ( vout + = note that the r1 is part of the compensation. it should be conformed to the feedback compensation. if the r1 is chosen, it should not be changed to adjust output voltage; only change r2 instead. using 1% or better resistors for the resistor divider is recommended. 495 . 0 x v tt v refsen = the vtt regulator voltage is determined by refsen voltage, and the internal fixed resistive divider from refsen to the ground divides the refsen voltage in the ratio of 1:1. the following equation can be used to calculate the vtt output voltage: vout r1 r2 0.8v comp fb f i g u r e 8 . r e s i s t o r d i v i d e r f o r v d d q a n d v m c h g a i n l c = 1 c esr s c l s c esr s 1 out out 2 out + + + t h e p o l e s a n d z e r o o f t h i s t r a n s f e r f u n c t i o n a r e : f l c = out c l 2 1 p f e s r = out c esr 2 1 p t h e f l c i s t h e d o u b l e p o l e s o f t h e l c f i l t e r , a n d f e s r i s t h e z e r o i n t r o d u c e d b y t h e e s r o f t h e o u t p u t c a p a c i t o r . l c out esr output phase f i g u r e 9 . t h e o u t p u t l c f i l t e r 505 . 0 x v tt v refsen = - source current - sink current output voltage setting the output voltage of the pwm converter can be adjusted with a resistive divider. the internal reference voltage is 0.8v. the following equation can be used to calculate the output voltage: vtt regulator input/output capacitor selection the input capacitor is chosen based on its voltage rating. under load transient condition, the input capacitor will momentarily supply the required transient current. the output capacitor for the vtt regulator is chosen to minimize any drop during load transient condition. higher capacitor value and lower esr reduce the output ripple and the load transiene drop. in addition, the capacitor is chosen based on its voltage rating. the recommended value of output capacitor is between 100 m f (min. esr rating is 8m w ) to 1000 m f (min. esr rating is 2m w ), and the maximum esr rating is 300m w . a low-esr aluminum electrolytic capacitor works well and provides good transient response and stability. p w m c o m p e n s a t i o n t h e o u t p u t l c f i l t e r o f a s t e p d o w n c o n v e r t e r i n t r o d u c e s a d o u b l e p o l e , w h i c h c o n t r i b u t e s w i t h ? 4 0 d b / d e c a d e g a i n s l o p e a n d 1 8 0 d e g r e e s p h a s e s h i f t i n t h e c o n t r o l l o o p . a c o m p e n s a t i o n n e t w o r k b e t w e e n c o m p , f b , a n d v o u t s h o u l d b e a d d e d t o c o m p e n s a t e t h e d o u b l e p o l e . t h e c o m p e n s a t i o n n e t w o r k i s s h o w n i n f i g u r e 1 2 . t h e o u t p u t l c f i l t e r c o n s i s t s o f t h e o u t p u t i n d u c t o r a n d o u t p u t c a p a c i t o r s . t h e t r a n s f e r f u n c t i o n o f t h e l c f i l t e r i s g i v e n b y : f esr f lc frequency -40db/dec -20db/dec f i g u r e 1 0 . t h e l c f i l t e r g a i n & f r e q u e n c y
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - s e p . , 2 0 0 9 a p w 7 1 1 6 w w w . a n p e c . c o m . t w 2 1 a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) t h e p w m m o d u l a t o r i s s h o w n i n f i g u r e 1 1 t h e i n p u t i s t h e o u t p u t o f t h e e r r o r a m p l i f i e r a n d t h e o u t p u t i s t h e p h a s e n o d e . t h e t r a n s f e r f u n c t i o n o f t h e p w m m o d u l a t o r i s g i v e n b y : g a i n p w m = osc in v v d v osc pwm comparator driver driver vcomp v in phase f i g u r e 1 1 . t h e p w m m o d u l a t o r t h e c o m p e n s a t i o n c i r c u i t i s s h o w n i n f i g u r e 1 2 . d e s i g n a a p p r o p r i a t e c o m p e n s a t i o n c i r c u i t t o g e t t h e d e s i r e d z e r o c r o s s o v e r f r e q u e n c y a n d s u f f i c i e n t p h a s e m a r g i n . t h e t r a n s f e r f u n c t i o n o f e r r o r a m p l i f i e r i s g i v e n b y : g a i n a m p = ? ? ? ? + ? ? ? ? + sc3 1 r3 // r1 sc2 1 r2 // sc1 1 = = out comp v v ( ) ? ? ? ? + ? ? ? ? + + ? ? ? ? ? + + ? ? ? ? + + c3 r3 1 s c2 c1 r2 c2 c1 s s c3 r3 r1 1 s c2 r2 1 s c1 r3 r1 r3 r1 t h e p o l e s a n d z e r o s o f t h e t r a n s f e r f u n c t i o n a r e : f z 1 = c2 r2 2 1 p f z 2 = ( ) c3 r3 r1 2 1 + p f p 1 = ? ? ? ? + p c2 c1 c2 c1 r2 2 1 f p 2 = c3 r3 2 1 p p w m c o m p e n s a t i o n ( c o n t . ) f i g u r e 1 2 . c o m p e n s a t i o n n e t w o r k v comp c2 v out r3 v ref c1 fb - + c3 r2 r1 t h e c l o s e d l o o p g a i n o f t h e c o n v e r t e r c a n b e w r i t t e n a s : g a i n l c x g a i n p w m x g a i n a m p f i g u r e 1 3 s h o w s t h e a s y m p t o t i c p l o t o f t h e c l o s e d l o o p c o n v e r t e r g a i n a n d t h e f o l l o w i n g g u i d e l i n e s w i l l h e l p t o d e s i g n t h e c o m p e n s a t i o n n e t w o r k . u s i n g t h e b e l o w g u i d e l i n e s s h o u l d g i v e a c o m p e n s a t i o n s i m i l a r t o t h e c u r v e p l o t t e d . a s t a b l e c l o s e d l o o p h a s a - 2 0 d b / d e c a d e s l o p e a n d a p h a s e m a r g i n g r e a t e r t h a n 4 5 d e g r e e . 1 . c h o o s e a v a l u e f o r r 1 , u s u a l l y b e t w e e n 1 k t o 5 k . 2 . s e l e c t t h e d e s i r e d z e r o c r o s s o v e r f r e q u e n c y f o : ( 1 / 5 ~ 1 / 1 0 ) x f s > f o > f e s r u s e t h e f o l l o w i n g e q u a t i o n t o c a l c u l a t e r 2 : 3 . p l a c e t h e f i r s t z e r o f z 1 b e f o r e t h e o u t p u t l c f i l t e r d o u b l e p o l e f r e q u e n c y f l c . f z 1 = 0 . 7 5 x f l c c a l c u l a t e t h e c 2 b y t h e e q u a t i o n : 4 . s e t t h e p o l e a t t h e e s r z e r o f r e q u e n c y f e s r : f p 1 = f e s r c a l c u l a t e t h e c 1 b y t h e e q u a t i o n : 1 r f f v v r2 lc o in osc d = 0.75 f r2 2 1 c2 lc p = 1 f c2 r2 c2 c1 esr - p = 2 5 . s e t t h e s e c o n d p o l e f p 2 a t h a l f o f t h e s w i t c h i n g f r e - q u e n c y a n d a l s o s e t t h e s e c o n d z e r o f z 2 a t t h e o u t - p u t l c f i l t e r d o u b l e p o l e f l c . t h e c o m p e n s a t i o n g a i n s h o u l d n o t e x c e e d t h e e r r o r a m p l i f i e r o p e n l o o p g a i n , c h e c k t h e c o m p e n s a t i o n g a i n a t f p 2 w i t h t h e c a p a - b i l i t i e s o f t h e e r r o r a m p l i f i e r .
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - s e p . , 2 0 0 9 a p w 7 1 1 6 w w w . a n p e c . c o m . t w 2 2 a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) p w m c o m p e n s a t i o n ( c o n t . ) f p 2 = 0 . 5 x f s f z 2 = f l c 1 2xf f r1 r3 lc s - = s f r3 1 c3 p = gain 0 f lc f esr f p2 =0.5f s f z1 =0.75f lc f o frequency pwm & filter gain compensation gain converter gain f z2 =f lc f p1 =f esr 20log (v in / v osc ) 20log (r2/r1) open loop error amp gain f i g u r e 1 3 . c o n v e r t e r g a i n & f r e q u e n c y in out s out in ripple v v l f v v i - = v out = i ripple x esr output inductor selection the inductor value determines the inductor ripple current and affects the load transient response. higher inductor value reduces the inductor?s ripple current and induces lower output ripple voltage. the ripple current and ripple voltage can be approximated by: where f s is the switching frequency of the regulator. although increases the inductor value to reduce the ripple current and voltage, there is a tradeoff existing between the inductor?s ripple current and the regulator load tran- sient response time. the maximum ripple current occurs at the maximum in- put voltage. a good starting point is to choose the ripple current to be approximately 30% of the maximum output current. once the inductance value has been chosen, select an inductor that is capable of carrying the required peak cur- rent without going into saturation. in some types of inductors, especially core that is make of ferrite, the ripple current will increase abruptly when it saturates. this will result in a larger output ripple voltage. output capacitor selection higher capacitor value and lower esr reduce the output ripple and the load transient drop. therefore, select high performance low esr capacitors are intended for switch- ing regulator applications. in some applications, mul- tiple capacitors have to be parallelled to achieve the de- sired esr value. a small decoupling capacitor in parallel for bypassing the noise is also recommended, and the voltage rating of the output capacitors also must be considered. if tantalum capacitors are used, make sure they are surge tested by the manufactures. if in doubt, consult the capacitors manufacturer. input capacitor selection the input capacitor is chosen based on the voltage rat- ing and the rms current rating. for reliable operation, select the capacitor voltage rating to be at least 1.3 times higher than the maximum input voltage. the maximum rms current rating requirement is approximately i out /2 , where i out is the load current. during power-up, the input capacitors have to handle large amount of surge current. if tantalum capacitors are used, make sure they are surge tested by the manufactures. if in doubt, consult the ca- pacitors manufacturer. for high frequency decoupling, a ceramic capacitor 1 m f can be connected between the drain of upper mosfet and the source of lower mosfet. mosfet selection a smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current. the selection of the n-channel power mosfets are de- termined by the r ds(on) , reverse transfer capacitance(c rss ) and maximum output current requirement. the losses in the mosfets have two components: conduction loss and transition loss. for the upper and lower mosfet, the losses are approximately given by the following equations: c o m b i n e t h e t w o e q u a t i o n s w i l l g e t t h e f o l l o w i n g c o m p o - n e n t c a l c u l a t i o n s :
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - s e p . , 2 0 0 9 a p w 7 1 1 6 w w w . a n p e c . c o m . t w 2 3 a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) mosfet selection (cont.) p upper = i out 2 (1+ tc)(r ds(on) )d + (0.5)(i out )(v in )(t sw )f s p lower = i out 2 (1+ tc)(r ds(on) )(1-d) where i out is the load current tc is the temperature dependency of r ds(on) f s is the switching frequency t sw is the switching interval d is the duty cycle note that both mosfets have conduction losses while the upper mosfet includes an additional transition loss. the switching internal, t sw , is the function of the reverse transfer capacitance c rss . the (1+tc) term is to factor in the temperature dependency of the r ds(on) and can be extracted from the ?r ds(on) vs temperature? curve of the power mosfet. layout consideration in high power switching regulator, a correct layout is im- portant to ensure proper operation of the regulator. in general, interconnecting impedances should be mini- mized by using short and wide printed circuit traces. sig- nal and power grounds are to be kept separating and finally combined to use ground plane construction or single point grounding. figure 14 illustrates the layout, with bold lines indicating high current paths; these traces must be short and wide. components along the bold lines should be placed close together. below is a checklist for your layout: the metal plate of the bottom of the packages (tssop-24p) must be soldered to the pcb and con- nect to the gnd plane on the backside through sev- eral thermal vias. more vias is better for heatsink. keep the switching nodes (ugate, lgate, and phase) away from sensitive small signal nodes since these nodes are fast moving signals. therefore, keep traces to these nodes as short as possible. connet the fb and vttfb to point of load and the refsen should be connected to the point of load of the vddq output. the traces from the gate drivers to the mosfets (ug1, lg1, ug2, and lg2) should be short and wide. decoupling capacitor, compensation component, the resistor dividers, boot capacitors, and ss capacitors should be close to their pins. the input capacitor should be near the drain of the upper mosfet; the output capacitor should be near the loads. the input capacitor gnd should be close to the out- put capacitor gnd and the lower mosfet gnd. the drain of the mosfets (vin and phase nodes) should be a large plane for heat sinking.
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - s e p . , 2 0 0 9 a p w 7 1 1 6 w w w . a n p e c . c o m . t w 2 4 q1 l1 c in APW7116 l o a d boot ss fb agnd c ss c vcc c boot q2 c out vcc lg ug gnd 5vdual 12v vddq v in vddq vtt vttgnd phase refsen load vttfb island on power plane via connection to ground plane bottom side pad a p p l i c a t i o n i n f o r m a t i o n ( c o n t . ) figure 14. layout guidelines
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - s e p . , 2 0 0 9 a p w 7 1 1 6 w w w . a n p e c . c o m . t w 2 5 p a c k a g e i n f o r m a t i o n t s s o p - 2 4 p note : 1. followed from jedec mo-153 adt. 2. dimension "d" does not include mold flash, protrusions or gate burrs. mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. dimension "e1" does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 10 mil per side. s y m b o l min. max. 1.20 0.05 0.09 0.20 7.70 7.90 0.15 a a1 c d e e l millimeters b 0.19 0.30 0.65 bsc tssop-24p 0.45 0.75 0.026 bsc min. max. inches 0.047 0.002 0.007 0.012 0.004 0.008 0.303 0.311 0.169 0.177 0.018 0.030 0 0.006 a2 0.80 1.05 4.30 4.50 e1 0.031 0.041 3.50 d1 0.138 e2 2.50 0.098 5.00 3.50 0.197 0.138 inches 8 o 0 o 8 o 0 o 0 view a 0 . 2 5 seating plane gauge plane see view a e 1 e b c a 2 a e a 1 l e 2 exposed pad d1 d 6.20 6.60 0.244 0.260
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - s e p . , 2 0 0 9 a p w 7 1 1 6 w w w . a n p e c . c o m . t w 2 6 c a r r i e r t a p e & r e e l d i m e n s i o n s h t1 a d a e 1 a b w f t p0 od0 b a0 p2 k0 b 0 section b-b section a-a od1 p1 application a h t1 c d d w e1 f 330.0 ? 2.00 50 min. 16.4+2.00 - 0.00 13.0+0.50 - 0.20 1.5 min. 20.2 min. 16.0 ? 0.30 1.75 ? 0.10 7.50 ? 0.10 p 0 p1 p 2 d 0 d1 t a 0 b 0 k 0 tssop - 24p 4.00 ? 0.10 8.00 ? 0.10 2.00 ? 0.10 1.5+0.10 - 0.00 1.5 min. 0.6+0. 00 - 0.40 6.9 ? 0.20 8.30. ? 0.20 1.50 ? 0.20 (mm) package type unit quantity tssop - 24p tape & reel 2000 d e v i c e s p e r u n i t
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - s e p . , 2 0 0 9 a p w 7 1 1 6 w w w . a n p e c . c o m . t w 2 7 t a p i n g d i r e c t i o n i n f o r m a t i o n tssop-24p user direction of feed c l a s s i f i c a t i o n p r o f i l e
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - s e p . , 2 0 0 9 a p w 7 1 1 6 w w w . a n p e c . c o m . t w 2 8 c l a s s i f i c a t i o n r e f l o w p r o f i l e s profile feature sn - pb eutectic assembly pb - free assembly preheat & soak temperature min (t smin ) temperature max (t smax ) time (t smin to t smax ) ( t s ) 100 c 150 c 60 - 120 seconds 150 c 200 c 60 - 1 2 0 seconds average ramp - up rate (t smax to t p ) 3 c/second ma x. 3 c/second max. liquidous temperature ( t l ) time at l iquidous (t l ) 183 c 60 - 150 seconds 217 c 60 - 150 seconds peak package body temperature (t p ) * see classification temp in table 1 see classification temp in table 2 time (t p ) ** within 5 c of the spec ified c lassification t emperature ( t c ) 2 0 ** seconds 3 0 ** seconds average r amp - down rate (t p to t smax ) 6 c/second max. 6 c/second max. time 25 c to p eak t emperature 6 minutes max. 8 minutes max. * tolerance for peak profile temperature (t p ) is defined a s a supplier minimum and a user maximum. ** tolerance for time at peak profile temperature (t p ) is defined as a supplier minimum and a user maximum. table 2. pb - free process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 350 - 2000 volume mm 3 >2000 <1.6 mm 260 c 260 c 260 c 1.6 mm ? 2.5 mm 260 c 250 c 245 c 3 2.5 mm 250 c 245 c 245 c table 1. snpb eutectic process ? classification temperatures (tc) package thickness volume mm 3 <350 volume mm 3 3 350 <2.5 mm 235 c 22 0 c 3 2.5 mm 220 c 220 c r e l i a b i l i t y t e s t p r o g r a m test item method description solderability jesd - 22, b102 5 sec, 245 c holt jesd - 22, a108 1000 hrs, bias @ 125 c pct jesd - 22, a102 168 hrs, 100 % rh, 2atm , 121 c tct jesd - 22, a104 500 cycles, - 65 c~150 c hbm mil - std - 883 - 3015.7 vhbm ? 2kv mm jesd - 22, a115 vmm ? 200v latch - up jesd 78 10ms, 1 tr ? 100ma
c o p y r i g h t ? a n p e c e l e c t r o n i c s c o r p . r e v . a . 4 - s e p . , 2 0 0 9 a p w 7 1 1 6 w w w . a n p e c . c o m . t w 2 9 c u s t o m e r s e r v i c e a n p e c e l e c t r o n i c s c o r p . head office : no.6, dusing 1st road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 t a i p e i b r a n c h : 2 f , n o . 1 1 , l a n e 2 1 8 , s e c 2 j h o n g s i n g r d . , s i n d i a n c i t y , t a i p e i c o u n t y 2 3 1 4 6 , t a i w a n t e l : 8 8 6 - 2 - 2 9 1 0 - 3 8 3 8 f a x : 8 8 6 - 2 - 2 9 1 7 - 3 8 3 8

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